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Integrated Circuit Systems, Inc.
ICS93735
DDR Phase Lock Loop Zero Delay Clock Buffer
Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: * Low skew, low jitter PLL clock driver * Max frequency supported = 266MHz (DDR 533) * I2C for functional and output control * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * 3.3V tolerant CLK_INT input Switching Characteristics: * CYCLE - CYCLE jitter (66MHz): <120ps * CYCLE - CYCLE jitter (>100MHz): <65ps * CYCLE - CYCLE jitter (>200MHz): <75ps * OUTPUT - OUTPUT skew: <100ps * Output Rise and Fall Time: 500ps - 700ps * DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
Functionality
INPUTS OUTPUTS AVDD CLK_INT CLKT CLKC FB_OUTT 2.5V (nom) L L H L 2.5V (nom) H H L H 2.5V (nom) < offset freq* offset freq* offset freq* offset freq* GND L L H L GND H H L H * The offset frequency is ~ 20 MHz, varying somewhat from part to part. PLL State on on off Bypassed/off Bypassed/off
48-Pin SSOP
Block Diagram
FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1
SCLK SDATA
Control Logic
CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5
FB_INT CLK_INT
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
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ICS93735
Pin Descriptions
PIN NUMBER PIN NAME TYPE PWR OUT OUT PWR IN IN PWR PWR OUT IN I/O Ground "Complementar y" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs. Power supply 2.5V Clock input of I2C input, 5V tolerant input "True" reference clock input, 3.3V tolerant input Not connected Analog power supply, 2.5V A n a l o g gr o u n d . "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. Data pin for I2C circuitr y 5V tolerant DESCRIPTION 1, 7, 8, 18, 24, 25, GND 31, 41, 42, 48 26, 30, 40, 43, 47, CLKC(9:0) 23, 19, 9, 6, 2 27, 29, 39, 44, 46, CLKT(9:0) 22, 20, 10, 5, 3 4, 11, 15, 21, 28, 34, 38, 45, 12 13 14, 32, 36 16 17 33 35 37 VDD SCLK CLK_INT N/C AVDD AGND FB_OUTT FB_INT SDATA
Byte 0: Output Control (1= enable, 0 = disable)
Byte 1: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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ICS93735
Byte 2: Reserved (1= enable, 0 = disable)
Byte 3: Reserved (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT PIN# PWD Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 4: Reserved (1= enable, 0 = disable)
Byte 5: Reserved (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 3,2 1 5,6 1 10, 9 1 20, 19 1 22, 23 1 27, 26 1 1 1
DESCRIPTION CLK0 (T&C) CLK1 (T&C) CLK2 (T&C) CLK3 (T&C) CLK4 (T&C) CLK9 (T&C) Reser ved Reser ved
Byte 6: Reserved (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 0 0 0 29, 30 1 39, 40 1 44, 43 1 46, 47 1 1
DESCRIPTION Reser ved (Note) Reser ved (Note) Reser ved (Note) CLK8 (T&C) CLK7 (T&C) CLK6 (T&C) CLK5 (T&C) Reser ved
Note: Don't write into these registers (7:5), writing into these registers can cause malfunction.
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ICS93735
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ICS (Slave/Receiver)
* * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK
Byte 6
Byte 6
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS93735
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND -0.5 V to VDD +0.5 V 0C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output parameters
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS RT = 120W, CL = 12 pF at 100MHz IDD2.5 Operating Supply Current RT = 120W, CL = 12 pF at 133MHz IDDPD CL=0 pF Output High Current IOH VDD = 2.5V, VOUT = 1V Output Low Current IOL VDD = 2.5V, VOUT = 1.2V High Impedance IOZ VDD = 2.7V, VOUT = VDD or GND Ouptut Current VDD = min to max, IOH = -1mA VOH High-level Output Voltage VDD = 2.3V, IOH = -12mA VDD = min to max, IOH = 1mA VOL Low-level Output Voltage VDD = 2.3V, IOH = 12mA 1 Output Capacitance VI = VDD or GND COUT 1. Guaranteed by design, not 100% tested in production. MIN TYP 236 263 -33 33 MAX 300 300 100 -29 37 10 2 2.25 1.95 0.05 0.3 3 UNITS mA mA mA mA mA V 0.1 0.4 V pF
-48 29
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ICS93735
Recommended Operation Conditions
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS AVDD Analog / Core Supply Voltag Input Voltage Level VIN Output Differential Pair 66/100/133/166MHz, VDD=2.50V VOC Crossing Voltage MIN 2.3 2 1.23 TYP 2.5 2.5 1.25 MAX 2.7 3 1.32 UNITS V V V
Timing Requirements
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 freqop Input Voltage level: 0-2.50V Operating Clock Frequency 1 dtin Input Clock Duty Cycle 1 Clock Stabilization tSTAB from VDD = 2.5V to 1% target frequency 1. Guaranteed by design, not 100% tested in production. MIN 22 40 TYP 50 MAX 340 60 100 UNITS MHz % s
Switching Characteristics
TA = 0 - 70C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated) PARAMETER Cycle to cycle Jitter1,2
1
SYMBOL tc-c
tpe Phase Error 1 Tskew 66 98 Output to output Skew Low-to-high level Propagation tPLH 3.67 3.68 1 Delay Time, Bypass Mode 1 Tskew Pulse Skew 1,3 DC no loads, 66 MHz to 167MHz 50.2 51.3 Duty Cycle (Sign Ended) 1 tR Single-ended 20-80 %; Load=120W/12pF 400 490 622 Rise Time 1 tF Single-ended 20-80 %; Load=120W/12pF 435 579 711 Fall Time 1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting period. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formular: duty_cycle=twH/tC, where the cycle time (tC)decreases as the frequency increases.
CONDITIONS 66 MHz 100 / 125 / 133 MHz 100MHz, input clock 0-2.5V, 0.8ns rise/fall input clock 0-2.5V, 0.8ns rise/fall CLK_IN to any output, 100MHz, Load = 120 W / 12 pF
MIN 46 27
TYP 52 33 -113
MAX 63 40
UNITS ps ps ps ns ps % ps ps
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ICS93735
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS93735yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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